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# LOONGSON232 events
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# The same event numbers mean different things on the two counters
#
event:0x00 counters:0 um:zero minimum:500 name:CYCLES : Cycles
event:0x01 counters:0 um:zero minimum:500 name:BRANCH_NUMBER : Branch instruction number 
event:0x02 counters:0 um:zero minimum:500 name:RESERVED : Reserved
event:0x03 counters:0 um:zero minimum:500 name:JR31_NUMBER : JR 31 number 
event:0x04 counters:0 um:zero minimum:500 name:IMEM_READ : Instruction memory read number 
event:0x05 counters:0 um:zero minimum:500 name:ISSUEBUS_VALID0 : Issue bus0 valid number
event:0x06 counters:0 um:zero minimum:500 name:ISSUEBUS_VALID1 : Issue bus1 valid number
event:0x07 counters:0 um:zero minimum:500 name:RESERVED : Reserved
event:0x08 counters:0 um:zero minimum:500 name:BHT : BHT intruction count
event:0x09 counters:0 um:zero minimum:500 name:MEM_READ : memory read count
event:0x0a counters:0 um:zero minimum:500 name:FETCH_STALLED : Cycles without instruction fetch
event:0x0b counters:0 um:zero minimum:500 name:REORDER_QUEUE_FULL : Reorder queue full count
event:0x0c counters:0 um:zero minimum:500 name:FLUSH_PIPELINE : Cycles cost in pipeline flush 
event:0x0d counters:0 um:zero minimum:500 name:TLBR_EXCP : TLBR exception count
event:0x0e counters:0 um:zero minimum:500 name:INTERRUPT : Interrupt count
event:0x0f counters:0 um:zero minimum:500 name:IQ_WRITE : Cycles cost in writing to instruction queue
event:0x10 counters:0 um:zero minimum:500 name:ICACHE_ACCESS : Instruction cache access count
event:0x11 counters:0 um:zero minimum:500 name:DCACHE_ACCESS : Data cache access count
event:0x12 counters:0 um:zero minimum:500 name:BRBUS_STATIC : Branch instruction staticly predicted
event:0x13 counters:0 um:zero minimum:500 name:LOADQ_FULL : Cycles stalled for full load queue
event:0x14 counters:0 um:zero minimum:500 name:STOREQ_FULL : Cycles stalled for full store queue
event:0x15 counters:0 um:zero minimum:500 name:MISSQ_FULL : Cycles stalled for full miss queue
event:0x16 counters:0 um:zero minimum:500 name:MISSREQQ_FULL : Cycles stalled for full miss request queue
event:0x17 counters:0 um:zero minimum:500 name:DTLB_ACCESS : Data TLB access count
event:0x18 counters:0 um:zero minimum:500 name:ITLB_ACCESS : Instruction TLB access count
event:0x19 counters:0 um:zero minimum:500 name:ALU1_EXEC :	 Number of instruction  executed in ALU1
event:0x1a counters:0 um:zero minimum:500 name:ALU2_EXEC :	 Number of instruction  executed in ALU2
event:0x1b counters:0 um:zero minimum:500 name:ADDR1_EXEC :	Number of instruction executed in ADDR1
event:0x1c counters:0 um:zero minimum:500 name:FLOAT1_EXEC : Number of instruction executed in FLOAT1
event:0x1d counters:0 um:zero minimum:500 name:DI_CONFICT : Counts of conflicts caused by data and inst mem-access
event:0x1e counters:0 um:zero minimum:500 name:STOREHEAD_STALL : Cycles stalled for store-q head not ok and full
event:0x1f counters:0 um:zero minimum:500 name:SL_CONFLICT : Counts of confilicts for the same d-cache line access by store and load 

event:0x20 counters:1 um:zero minimum:500 name:COMMITTED_ISSUED : Committed instruction count
event:0x21 counters:1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted count
event:0x22 counters:1 um:zero minimum:500 name:CYCLES : Cycles
event:0x23 counters:1 um:zero minimum:500 name:JR31_MISPREDICTED : JR31 mispredicted count
event:0x24 counters:1 um:zero minimum:500 name:DMEM_VALID : Data memory access counts
event:0x25 counters:1 um:zero minimum:500 name:RESERVED : Reserved
event:0x26 counters:1 um:zero minimum:500 name:RESERVED : Reserved
event:0x27 counters:1 um:zero minimum:500 name:DUNCACHE_VALID :Data uncache access counts 
event:0x28 counters:1 um:zero minimum:500 name:BHT_MISSES : BHT misses
event:0x29 counters:1 um:zero minimum:500 name:MEM_WRITE : Memory write counts
event:0x2a counters:1 um:zero minimum:500 name:REMAIN : Remain
event:0x2b counters:1 um:zero minimum:500 name:BRANCH_QUEUE_FULL : Branch queue full count
event:0x2c counters:1 um:zero minimum:500 name:REMAIN : Remain
event:0x2d counters:1 um:zero minimum:500 name:EXCEPTION : Total exception count
event:0x2e counters:1 um:zero minimum:500 name:REMAIN : Remain
event:0x2f counters:1 um:zero minimum:500 name:INSTQ_WRITE : Number of instruction write to queue
event:0x30 counters:1 um:zero minimum:500 name:ICACHE_HIT : Instruction cache hit count
event:0x31 counters:1 um:zero minimum:500 name:DCACHE_HIT : Data cache hit count
event:0x32 counters:1 um:zero minimum:500 name:BR_STATIC_MISSES : Branch staticly mispredicted count
event:0x33 counters:1 um:zero minimum:500 name:ICACHE_WAY_HIT : Instruction cache way predict hit count
event:0x34 counters:1 um:zero minimum:500 name:ICACHE_WAY_UPDATE : Insrtuction cache way update count
event:0x35 counters:1 um:zero minimum:500 name:INST_FETCHED : Number of instruction fetched
event:0x36 counters:1 um:zero minimum:500 name:INST_STALL : Cycles stalled for instrucion cache miss
event:0x37 counters:1 um:zero minimum:500 name:DTMISS_JTHIT :Miss in DTLB but hit in JTLB count
event:0x38 counters:1 um:zero minimum:500 name:ITMISS_JTHIT :Miss in ITLB but hit in JTLB count
event:0x39 counters:1 um:zero minimum:500 name:COMMIT_BUS0 : Number of instructions commited on bus0
event:0x3a counters:1 um:zero minimum:500 name:COMMIT_BUS1 : Number of instructions commited on bus1
event:0x3b counters:1 um:zero minimum:500 name:HAS_COMMIT : Cycles have instruction commit
event:0x3c counters:1 um:zero minimum:500 name:COMMIT_TWO : Cycles have two instruction committed
event:0x3d counters:1 um:zero minimum:500 name:DATA_INTER_CONFLICT :Conflict count for different data-type access
event:0x3e counters:1 um:zero minimum:500 name:SL_COMMIT : Load and store committed
event:0x3f counters:1 um:zero minimum:500 name:REMAIN : Remain
